FIELD OF THE INVENTION
The invention relates to an integrated memory having a reference potential, and to an operating method for such a memory.
U.S. Pat. Nos. 5,844,832 and 5,822,237 describe ferroelectric memories of the FRAM or FeRAM type (Ferroelectric Random Access Memory) of the 1-transistor/1-capacitor type. Such memories are constructed similarly to DRAMs (Dynamic Random Access Memories) but their storage capacitors have a ferroelectric dielectric. Their bit lines are connected in pairs to differential sense amplifiers. In the event of a read access, a datum is transferred from one of the memory cells to the sense amplifier via one of the bit lines of the bit line pairs, while a reference potential is generated on the other bit line of the bit line pair. The sense amplifier subsequently amplifies the differential signal present at its inputs to full logic levels.
In the circuits described in the two U.S. patents, the reference potential is generated by different states being stored in two reference memory cells connected to different bit lines. This means that the ferroelectric dielectric of the storage capacitors of the reference memory cells, which are constructed in exactly the same way as the normal memory cells of the memory, is polarized differently. Afterwards, the states stored in the reference memory cells are read out onto the associated bit lines and the two bit lines are short-circuited, with the result that a common reference potential is finally established on both bit lines.
According to U.S. Pat. No. 5,844,832, firstly the reference memory cells are read onto the associated bit lines by their selection transistors being turned on via a reference word line, and then the two bit lines are short-circuited in order to generate the reference potential. According to U.S. Pat. No. 5,822,237 the bit lines are short-circuited during a period of time in which the selection transistors of the reference memory cells are also in the on state. In another variant presented in U.S. Pat. No. 5,822,237, the short-circuiting transistor connects to one another not the two bit lines that are connected to the reference memory cells, but, within the reference memory cells, directly the storage capacitors thereof. In that variant, in order to generate the reference potential, firstly the short-circuiting transistor is turned on, so that charge balancing takes place between the two reference memory cells, before the reference word line is activated and the selection transistors of the reference memory cells are turned on. Before the selection transistors are turned on, the short-circuiting transistor is turned off.
In those prior art memories in which the short-circuiting of the bit lines or reference memory cells and the turning-on of their selection transistors are effected successively, a relatively long time period is required for generating the reference potential. In the other above-mentioned prior art memories, the selection transistors of the reference memory cells are in the on state the whole time while the short-circuiting transistor is in the on state and carries out complete charge balancing between the bit lines. This has the disadvantage that, during the charge balancing, the non-linear capacitances of the ferroelectric storage capacitors of the reference memory cells affect the reference potential to be generated. By contrast, the bit line capacitances are linear. In memories in which firstly the reference memory cells are read onto the bit lines and, after their selection transistors have been turned off, then the bit lines are short-circuited, a reference potential is established on the bit lines which corresponds to the arithmetic mean of the potentials established on the bit lines during the reading of the reference memory cells. As a result of the non-linear capacitances of the storage capacitors, by contrast, a different value of the reference potential is produced if the selection transistors and the short-circuiting transistor are simultaneously in the on state.